1. Field of the Invention
The present invention generally relates to a symbol timing synchronization method and apparatus, in particular, to a fine symbol timing synchronization method and apparatus in an orthogonal frequency-division multiplexing (OFDM) system.
2. Description of Related Art
In an orthogonal frequency-division multiplexing (OFDM) system, a multi-carrier modulation technique is applied, and a channel is divided into a plurality of orthogonal sub-channels. Therefore, through the OFDM system, a high-speed data flow may be converted into parallel low-speed sub-data flows, and these parallel low-speed sub-data flows are modulated so as to be transmitted over each sub-channel. The above orthogonal signals may be separated by a relevant modulation technique at a receiving end, such that an inter-channel-interference (ICI) may be effectively reduced. In addition, since a signal bandwidth on each sub-channel is smaller than the bandwidth of the whole transmission channel, an inter-symbol-interference (ISI) can be reduced or eliminated.
The OFDM system is capable of effectively resisting the multi-path time-delay spread and has a high spectrum utility factor, but also has a disadvantage of being sensitive to synchronization errors. The synchronization error mainly includes carrier frequency offset, sampling clock offset, and symbol timing synchronization offset. The symbol timing synchronization offset may result in the ISI and ICI, and seriously affect the demodulation system.
The OFDM technique is widely applied in digital broadcasting systems, for example, in a digital video broadcasting-terrestrial (DVB-T) system. Referring to FIG. 1, a systematic block diagram of a DVB-T system 100 is shown. The DVB-T system 100 includes a transmitter 101 and a receiver 102. After receiving a symbol signal, the transmitter 101 processes the symbol signal, and transmits the processed symbol signal to the receiver 102 through a wireless channel 17. Then, the receiver 102 receives the symbol signal from the wireless channel 17 and processes the received symbol signal, so as to decode the symbol signal transmitted by the transmitter 101.
The transmitter 101 includes a pilot and transmission parameter signaling (TPS) inserter 11, a guard interval (GI) inserter 12, an inversed fast Fourier transformer 13, a cyclic prefix (CP) inserter 14, a digital-to-analog converter 15, and a transmitter front-end circuit 16. The receiver 102 includes a receiver front-end circuit 18, an analog-to-digital converter 19, a down-conversion and anti-aliasing filter circuit 20, an interpolator 21, a frequency and phase offset corrector 22, a coarse symbol timing synchronization apparatus 23, a CP remover 24, a fast Fourier transformer 25, a TPS acquisition circuit 26, a channel estimation and equalization circuit 27, a fine symbol timing synchronization apparatus 28, a carrier synchronization apparatus 29, and a sampling synchronization apparatus 30.
First, the transmitter 101 receives a frequency domain symbol signal. The pilot and TPS inserter 11 inserts a plurality of scattered pilots and TPSs into the received frequency domain symbol signal. The GI inserter 12 inserts a GI into its received input signal (performing a zero padding on two ends of a frequency band of this received input signal). Afterward, the inversed fast Fourier transformer 13 performs an inversed fast Fourier transform (IFFT) on its received input signal (frequency domain signal), so as to generate an output signal (time domain signal).
Next, the CP inserter 14 inserts a CP into its received input signal. Then, the digital-to-analog converter 15 converts its received input signal (digital signal) into an analog output signal. The transmitter front-end circuit 16 processes its received input signal (base band analog signal) to generate an output signal (radio-frequency analog signal), and transmits the output signal to the receiver 102 through the wireless channel 17.
The receiver front-end circuit 18 receives the output signal transmitted by the transmitter 10 through the wireless channel 17, and then processes its received input signal. Next, the analog-to-digital converter 19 converts its received input signal (analog signal) into a digital signal. After that, the down-conversion and anti-aliasing filter circuit 20 performs down-conversion, anti-aliasing, and filtering operations on its received input signal (digital signal).
The interpolator 21 receives a synchronous sampling signal generated by the sampling synchronization apparatus 30, and performs an interpolation operation on the output signal of the down-conversion and anti-aliasing filter circuit 20 according to the synchronous sampling signal. The frequency and phase offset corrector 22 performs a frequency and phase offset correction on the output signal of the interpolator 22 according to a synchronous carrier signal generated by the carrier synchronization apparatus 29.
Then, the coarse symbol timing synchronization apparatus 23 performs a coarse symbol timing synchronization on the output signal of the frequency and phase offset corrector 22, and accordingly adjusts a time delay offset of the output signal of the frequency and phase offset corrector 22, such that the output signal of the frequency and phase offset corrector 22 roughly falls in a correct fast Fourier transform (FFT) window. The CP remover 24 adjusts a time delay of the output signal of the coarse symbol timing synchronization apparatus 23 according to the output signal of the fine symbol timing synchronization apparatus, and accurately removes the CP of the output signal of the coarse symbol timing synchronization apparatus 23. Afterward, the fast Fourier transformer 25 performs an FFT on the output signal (time domain signal) of the CP remover 24, so as to generate a frequency domain output signal.
The fine symbol timing synchronization apparatus 28 performs a fine symbol timing synchronization on the output signal of the fast Fourier transformer 25, so as to obtain an accurate time delay of its received input signal, such that the fine symbol timing synchronization apparatus 28 enables the CP remover 24 to find a correct starting position of the FFT window when removing the CP. The carrier synchronization apparatus 29 performs a carrier synchronization on the output signal of the fast Fourier transformer 25 to obtain a correct synchronous carrier signal. The sampling synchronization apparatus 30 performs a sampling synchronization on the output signal of the fast Fourier transformer 25 to obtain the correct synchronous sampling signal.
Then, the TPS acquisition circuit 26 acquires the TPS in the output signal of the fast Fourier transformer 25. Finally, the channel estimation and equalization circuit 27 performs channel estimation and equalization operations on its received input signal, and outputs an equalized signal to the back-end circuit connected to the receiver 102.
In order to effectively eliminate the complicated multi-path effect, the CP is inserted in the OFDM system to reduce the interference of the multi-path effect. That is, the OFDM system replicates the data behind the symbol signal to the front-end of the symbol signal to serve as the GI, so as to reduce the interference on the output signal of the transmitter coming from a plurality of paths of the wireless channel.
The symbol timing synchronization is generally divided into two stages, namely, fine symbol timing synchronization and coarse symbol timing synchronization. The fine symbol timing synchronization is performed after the FFT, for detecting a residual symbol synchronization offset, so as to accurately lock the starting position of the FFT window on the starting position of the symbol signal of a first path. The coarse symbol timing synchronization is performed before the FFT, and the starting position of the symbol signal is determined through the autocorrelation of the CP. When the signal to noise ratio (SNR) is low, the accuracy of the coarse symbol timing synchronization is also low.
FIGS. 2A and 2B respectively show starting positions of FFT windows 211 and 311 in a multi-path channel. In FIGS. 2A and 2B, the starting positions of the FFT windows 211 and 311 are not synchronous, and the symbol timing synchronization technique is employed to estimate the correct starting position of each FFT window. In the multi-path channel, the correct starting position of the FFT window is equal to the starting position of the symbol signal of the first path. Therefore, since the starting position of the FFT window is accurately locked on the starting position of the symbol signal of the first path, the CP remover is enabled to accurately remove the CP. Referring to FIG. 2A, in the multi-path channel, a symbol signal 201 of the first path and a symbol signal 202 of a second path are provided, and the dashed areas are CPs 203 and 204 of the symbol signals. Generally, in the conventional symbol timing synchronization method, the starting position of the symbol signal 201 of the first path, instead of the starting position of the symbol signal 202 of the second path, is set as the correct starting position of the FFT window 211.
Referring to FIG. 2B, the energy of a symbol signal 301 of the first path is smaller than that of a symbol signal 302 of the second path. Due to multi-path attenuation, in the conventional symbol timing synchronization method, the starting position of the FFT window is locked on the starting position of the maximum path. Therefore, in this example, the starting position of the FFT window 311 is locked on the starting position of the symbol signal 302 of the second path instead of the starting position of the symbol signal 301 of the first path. When the starting position of the FFT window 311 is locked on the false position, a severe failure may occur to the back-end circuit during the subsequent channel estimation and equalization operations, thus affecting the receiving performance of the receiver.
FIG. 3 is a systematic block diagram of the fine symbol timing synchronization apparatus 28 in the DVB-T system 100. The fine symbol timing synchronization apparatus 28 adopts the conventional fine symbol timing synchronization method to find the correct FFT window according to a channel impulse response estimated by the receiver 102. The fine symbol timing synchronization apparatus 28 includes a scattered pilot extraction circuit 284, an inversed fast Fourier transformer 286, and an FFT window estimation circuit 288.
Referring to FIGS. 1 and 3 together, the CP remover 24 removes the CP of the output signal of the coarse symbol timing synchronization apparatus 23 according to the starting position of the FFT window found by the fine symbol timing synchronization apparatus 28. The scattered pilot extraction circuit 284 receives the output signal of the fast Fourier transformer 25, and extracts a plurality of scattered pilots from its received input signal. Next, the scattered pilot extraction circuit 284 calculates a channel frequency response according to the scattered pilots, and outputs the channel frequency response to the inversed fast Fourier transformer 286. The inversed fast Fourier transformer 286 performs an IFFT on the channel frequency response to obtain the channel impulse response. After that, the FFT window estimation circuit 288 finds the position with the energy exceeding the threshold first or the position with the maximum energy as the starting position of the symbol signal in the channel impulse response from the inversed fast Fourier transformer 286, and locks the starting position of the FFT window on the position found by the FFT window estimation circuit 28. If the FFT window is accurately locked on the position of the first path, the receiver may reduce the interference resulted from the synchronization error in the multi-path channel, such as ICI and ISI.
To be brief, in the conventional fine symbol timing synchronization method, the fine symbol timing synchronization is performed based on the first path in the channel impulse response, and the first path may be the path with the energy exceeding the threshold first or the maximum path with the maximum energy. Besides, in the conventional symbol timing synchronization method, the path with the minimum noise power in the channel impulse response is found as the first path, and such a method for founding the first path is called a noise power method.
The synchronization time of the fine symbol timing synchronization method, in which finding the path with the energy exceeding the threshold first or the maximum path with the maximum energy in the channel impulse response as the first path, is relatively short. However, when the energy of the symbol signal of the first path is smaller than that of the symbol signal of the second path, the conventional fine symbol timing synchronization method may mistake the second path as the first path, thus affecting the performance of the whole receiver.
Though the fine symbol timing synchronization method by taking the path with the minimum noise power in the channel impulse response as the first path may solve the problem that the energy of the symbol signal of the first path is smaller than that of the symbol signal of the second path, the complexity of a feedback circuit needed for calculating the noise power is quite high, so the required synchronization time is relatively long. Generally, in an 8K mode of the DVB-T system, the synchronization time is approximately tens of milliseconds. Further, in the multi-path channel, the energies of the symbol signals of certain paths are much smaller than that of the symbol signal of the maximum path (usually with a difference of more than 18 dB), and their SNR values are quite low, such that the conventional fine symbol timing synchronization method becomes inaccurate, and false determination may occur.
To sum up, under the circumstance that the SNR is relatively low, if the symbol signal is transmitted in the wireless channel with multi-path attenuation, it is difficult for the receiver employing the conventional fine symbol timing synchronization method to stably detect the correct synchronization position of the symbol signal.